1. Field of the Invention
The present invention relates to a memory device, and more particularly to a highly reliable memory device with high performance in read, write and erase.
2. Description of the Prior Art
With the development of memory technology, the storage capacity for a memory device is also increased, while the cost for each byte of storage space of the memory device is correspondingly reduced. Therefore, enhancing the processing performance, reliability of the memory device, and ensuring accurate, fast and safe operation of the data have become our main goal.
Referring to FIG. 1A, a prior art memory device is reading a page of data from a memory array. Since the IS (instruction) inputted in the memory device 11 includes a command code 11a, an address code 11b, and a confirm code C. The address code 11b provides access to the page buffer 11d of a memory array 11c and read access to the data stream of the memory array 11c, and the confirm code C enables the execution of reading.
FIG. 1B shows that a prior art memory device 11 is reading a page of data from two memory arrays. The execution of reading of two memory arrays 11c and 12c, the inputted instruction must comprises two command codes 11a and 12a, and two address codes 11b and 12b. The two address codes 11b and 12b provide access to the page buffers 11d and 12d of the memory arrays 11c and 12c, respectively, for the execution of the reading of the data stream of the memory arrays 11c and 12c. Therefore, it will take more time for the memory device 11 to process the inputted instruction.
Similarly, as shown in FIGS. 1C-1F, wherein FIG. 1C shows that the prior art memory device is programming data into a page of a memory array, FIG. 1D shows that the prior art memory device is programming data into a page of two memory arrays, FIG. 1E shows that the prior art memory device erases data from a memory array, and FIG. 1F shows that the prior art memory device erases data from two memory arrays. The operation theory of FIGS. 1C-1F is the same as FIGS. 1A and 1B, further explanation would be omitted. Hence, it is impossible for the existing memory devices to perform read, program or erase to multiple memories with only a single instruction. The data accuracy in the memory cannot be guaranteed if mistakes or errors occur during reading and writing, and therefore, the existing flash memory devices are unreliable.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.